The present invention relates to a differential amplifier circuit of a semiconductor integrated circuit.
As a conventional differential amplifier circuit, there has been known a circuit shown in FIG. 5. That is, the conventional differential amplifier circuit is made up of a differential stage having input terminals 1, 2 a differential pair 100 including enhancement made P-MOS transistors 102 and 103 sources of which are connected to each other, a constant current source regions 106 one end of which is connected to the source of the differential pair and the other end of which is connected to a power supply Vdd, and a current mirror circuit 101 including enhancement mode N-MOS transistors 104 and 105. The gate of the enhancement mode P-MOS transistor 102 forming the differential pair 100 is connected to a non-inverted input terminal 1 whereas the gate of the enhancement mode P-MOS transistor 103 is connected to an inverted input terminal 2, and the respective drains of the enhancement mode P-MOS transistor 103 of the differential pair and the enhancement mode N-MOS transistor 105 of the current mirror circuit 101 are connected to an output 3.
In the case where a voltage VINP of the non-inverted input terminal 1 is larger than a voltage VINN of the inverted input terminal 2, a voltage VOUT of the output terminal 3 has a "HIGH" level, whereas in the case where VINP is smaller than VINN, VOUT has a "LOW" level.
The conventional differential amplifier circuit shown in FIG. 5 allows an offset voltage of about 10 mV to be developed, which leads to a serious defect of the CMOS differential amplifier circuit.
Also, in the conventional differential amplifier circuit shown in FIG. 5, in the case where the voltage at the non-inverted input terminal 1 or the inverse input terminal 2 is near GND, the enhancement mode P-MOS transistor 102 or 103 that forms the differential pair becomes in a non-saturated state, which leads to problems such as the more deterioration of offset voltage, the lowering of an operation speed, or an abnormality in operation.